Videos

A curated collection of high-quality moving color pictures with sound covering some of the most important topics known to mankind such as FuseSoC, Edalize and SERV

FuseSoC & Edalize

FuseSoC Packaging Goes Public, ORConf 2025, Valencia, Spain
FuseSoC Packaging Goes Public
ORConf 2025, Valencia, Spain
The Future of FuseSoC, ORConf 2024, Gothenburg, Sweden
The Future of FuseSoC
ORConf 2024, Gothenburg, Sweden
Beyond EDA lies Edalize, Latch-Up 2024, Cambridge, MA
Beyond EDA lies Edalize
Latch-Up 2024, Cambridge, MA
FuseSoC in Three Minutes, ORConf 2023, Munich, Germany
FuseSoC in Three Minutes
ORConf 2023, Munich, Germany
Edalize it. Don't critizise it, WOSET 2020, Online
Edalize it. Don't critizise it
WOSET 2020, Online
A CPU is Only as Good as its Ecosystem: Turning RISC-V CPUs into Systems with FuseSoC - RISC-V week 2022, Paris, France
A CPU is Only as Good as its Ecosystem
RISC-V week 2022, Paris, France
FuseSoC - Cores have never been so much fun - Latch-Up 2019, Zurich, Switzerland
FuseSoC - Cores have never been so much fun
Latch-Up 2019, Zurich, Switzerland
FuseSoC - Cores have never been so much fun - Latch-Up 2019, Portland, Oregon
FuseSoC - Cores have never been so much fun
Latch-Up 2019, Portland, Oregon
FuseSoC - From being conFuse(SoC)d to being oF use (SoC) after a Few SoC
From being conFuse(SoC)d to being oF use(SoC) after a Few SoC
ORConf 2017, Hebden Bridge, UK
FuseSoC, ORConf 2016, Bologna, Italy
FuseSoC
ORConf 2016, Bologna, Italy
Hands off the cores! Hands-on with ORPSoCv3, ORConf 2013, Cambridge, UK
Hands off the cores! Hands-on with ORPSoCv3
ORConf 2013, Cambridge, UK
ORPSoCv3 - Solving the core issue, ORConf 2012, Stockholm, Sweden, UK
ORPSoCv3 - Solving the core issue
ORConf 2012, Stockholm, Sweden

SERV

Corescore like never before, Latch-Up 2024, Cambridge, MA
Corescore like never before
Latch-Up 2024, Cambridge, MA
A quick talk about a small CPU, ORConf 2023, Munich, Germany
A quick talk about a small CPU
ORConf 2023, Munich, Germany
SERV: 32-bit is the New 8-bit, RISC-V Summit 2022, San Jose, CA
SERV: 32-bit is the New 8-bit
RISC-V Summit 2022San Jose, CA
SERV: RISC-V for a Fistful of Gates, RISC-V Embedded Forum 2021, Online
SERV: RISC-V for a Fistful of Gates
RISC-V Embedded Forum 2021, Online
SERV introduction movie, 1st Virtual Munich RISC-V Meetup 2020, Online
SERV introduction movie
1st Virtual Munich RISC-V Meetup 2020, Online
Bit by bit - How to fit 8 RISC V cores in a $38 FPGA board, RISC-V Workshop 2019, Zürich, Switzerland
Bit by bit - How to fit 8 RISC V cores in a $38 FPGA board
RISC-V Workshop 2019, Zürich, Switzerland